The disclosed invention generally relates to all capacitive analog-to-digital (A/D) converters, and is particularly directed to an all capacitive A/D converter which utilizes selectively switched parallel capacitors of substantially identical value.
Analog-to-digital (A/D) converters are utilized in systems wherein analog signals, such as those provided by analog transducers, are processed digitally. The resolution of a particular A/D converter increases with the number of output bits, and the resolution will depend upon the required dynamic range of the particular application.
While the need for accurate high resolution A/D converters has existed for some time, the attempts to meet such needs have not been satisfactory. With known A/D converter techniques which utilize binary weighted elements, maintaining monotonicity with increased resolution becomes more difficult. Particularly, as the number of bits increases the requirement of matching circuit elements quickly becomes more stringent. An example of the use of binary weighted elements is set forth in U.S. Pat. No. 4,129,863, issued to Gray, et al. on Dec. 12, 1978, which utilizes binary weighted capacitors.
With monolithic integrated circuitry the stringent matching requirement may be addressed by increasing the dimensions of precision ratioed elements to reduce mismatching. However, increasing element dimensions reduces yield.
Another approach to meeting the stringent matching requirement is the use of precision thin film precision resistors and on-chip laser trimming. However, besides being more complex, laser trimming may affect the temperature tracking characteristics of the resistors.
A particular approach to dealing with the matching requirement is set forth in a paper "High-Resolution A/D Conversion in MOS/LSI," IEE Journal of Solid State physics, Fotouhi et al, Vol. SC-14, No. 6, Dec. 1979, pp. 920-926. The technique disclosed therein combines a string of equal valued diffused resistors and a binary ratioed capacitor array to achieve 12 bit monotonicity while requiring 8 bit ratio accurate circuit elements. However, the matching of resistors is usually more complex than the matching of capacitors. A similar technique is set forth in U.S. Pat. No. 4,200,863, issued to Hodges, et al. on Apr. 29, 1980.
Another particular approach is set forth in a paper "A Monolithic 12b 3us ADC," McGlinchey, 1982 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 80-81. The technique disclosed therein utilizes parallel equal valued current sources for the most significant bits. However, such technique is necessarily more complex because of the use of active devices.
Yet another known approach involves the use of parallel equal valued resistors for the most significant bits. However, matching resistors is usually more difficult than matching capacitors.